1. Field of the Invention
The invention relates to a memory device and a method of fabricating the same. More particularly, the invention relates to a non-volatile memory device and a method of fabricating the same.
2. Description of Related Art
Non-volatile memory devices are capable of storing, reading, and erasing data repeatedly and have the advantage of retaining the stored data even after the system is powered off. Therefore, the non-volatile memory devices have been extensively applied to personal computers and electronic equipment.
A typical non-volatile memory device includes a floating gate and a control gate. The control gate is formed directly on the floating gate and is separated from the floating gate by a dielectric layer. Besides, the floating gate is separated from a substrate by a tunneling oxide layer. This device is commonly known as a stacked gate flash memory device.
When data are erased from the non-volatile memory, it is difficult to control the quantity of electrons ejected from the floating gate, and thus excessive electrons may be ejected from the floating gate. Thereby, the floating gate may have a net positive charge, which refers to as the “over-erasing” phenomenon. When the over-erasing phenomenon is severe, the channel underneath the floating gate may be turned on before an operating voltage is applied to the control gate. As a result, reading errors may occur. In order to solve the over-erasing issue, split gate non-volatile memories have been introduced. The split gate non-volatile memory includes the control gate, the floating gate, and a selecting gate (i.e., an erasing gate) that is located on a sidewall of the control gate, on a sidewall of the floating gate, and above the substrate. The selecting gate (i.e., the erasing gate) is separated from the control gate, the floating gate, and the substrate by a gate dielectric layer. With this configuration, even when the over-erasing problem is so severe that the channel underneath the floating gate keeps open in the absence of an operating voltage applied to the control gate, the channel underneath the selecting gate is still closed. Thus, the drain/source region 114 cannot be turned on, and the data read-out errors can be prevented.
Based on Flower-Nordheim (FN) tunneling, which is a common way to erase data, carriers can flow between the floating gate and the erasing gate. However, the strength of electric field between the floating gate and the erasing gate is relevant to the side profile of the floating gate. Since it is difficult to control the fabrication of the side profile of the floating gate, the erasing efficiency cannot consistently remain high.